The present invention relates generally to apparatus for providing capacitance to an electronic circuit, and more particularly to embedded capacitors in an integrated circuit package, and methods of capacitor and package fabrication.
Electronic circuits, and particularly computer and instrumentation circuits, have in recent years become increasingly powerful and fast. As circuit frequencies continue to escalate, with their associated high frequency transients, noise in the power and ground lines increasingly becomes a problem. This noise can arise due to inductive and capacitive parasitics, for example, as is well known. To reduce such noise, capacitors known as decoupling capacitors are often used to provide a stable signal or stable supply of power to the circuitry.
Capacitors are further utilized to dampen power overshoot when an electronic device (e.g., a processor) is powered up, and to dampen power droop when the device begins using power. For example, a processor that begins performing a calculation may rapidly need more current than can be supplied by the on-chip capacitance. In order to provide such capacitance and to dampen the power droop associated with the increased load, off-chip capacitance should be available to respond to the current need within a sufficient amount of time. If insufficient voltage is available to the processor, or if the response time of the capacitance is too slow, the die voltage may collapse. The localized portions of a die that require large amounts of current in short periods of time are often referred to as die xe2x80x9chot spots.xe2x80x9d
Decoupling capacitors and capacitors for dampening power overshoot or droop are generally placed as close as practical to a die load or hot spot in order to increase the capacitors"" effectiveness. Often, the decoupling capacitors are surface mounted to the die side or land side of the package upon which the die is mounted. FIG. 1 illustrates a cross-section of an integrated circuit package 102 having die side capacitors 106 and land side capacitors 108 in accordance with the prior art. Die side capacitors 106, as their name implies, are mounted on the same side of the package as the integrated circuit die 104. In contrast, land side capacitors 108 are mounted on the opposite side of the package 102 as the die 104.
FIG. 2 illustrates an electrical circuit that simulates the electrical characteristics of the capacitors illustrated in FIG. 1. The circuit shows a die load 202, which may require capacitance or noise dampening in order to function properly. Some of the capacitance can be supplied by capacitance 204 located on the die. Other capacitance, however, must be provided off chip, as indicated by off-chip capacitor 206. The off-chip capacitor 206 could be, for example, the die side capacitors 106 and/or land side capacitors 108 illustrated in FIG. 1. The off-chip capacitor 206 may more accurately be modeled as a capacitor in series with some resistance and inductance. For ease of illustration, however, off-chip capacitance 206 is modeled as a simple capacitor.
Naturally, the off-chip capacitor 206 would be located some distance, however small, from the die load 202, due to manufacturing constraints. Accordingly, some inductance 208 exists between the die load and the off-chip capacitance. Because the inductance 208 tends to slow the response time of the off-chip capacitor 206, it is desirable to minimize the electrical distance between the off-chip capacitance 206 and the die load 202, thus reducing the inductance value 208. This can be achieved by placing the off-chip capacitor 206 as electrically close as possible to the die load.
Referring back to FIG. 1, die side capacitors 106 are mounted around the perimeter of the die 104, and provide capacitance to various points on the die through traces and vias (not shown) and planes in the package 102. Because die side capacitors 106 are mounted around the perimeter of the die, the path length between a hot spot and a capacitor 106 may result in a relatively high inductance feature between the hot spot and the capacitor 106.
In contrast, land side capacitors 108 can be mounted directly below die 104, and thus directly below some die hot spots. Thus, in some cases, land side capacitors 108 can be placed electrically closer to the die hot spots than can die side capacitors 106, resulting in a lower inductance path to between the die hot spot and the capacitance 108. However, the package also includes connectors (not shown), such as pins or lands, located on its land side. In some cases, placement of land side capacitors 108 on the package""s land side would interfere with these connectors. Thus, the use of land side capacitors 108 is not always an acceptable solution to the inductance problem.
Besides the inductance issues described above, additional issues are raised by the industry""s trend to continuously reduce device sizes and packing densities. Because of this trend, the amount of package real estate available to surface-mounted capacitors is becoming smaller and smaller.
As electronic devices continue to advance, there is an increasing need for higher levels of capacitance at reduced inductance levels for decoupling, power dampening, and supplying charge. In addition, there is a need for capacitance solutions that do not interfere with package connectors, and which do not limit the industry to certain device sizes and packing densities. Accordingly, there is a need in the art for alternative capacitance solutions in the fabrication and operation of electronic devices and their packages.